The invention relates to digital-to-analog converters, and particularly to an improved interpolation digital-to-analog converter of the type generally described in U.S. Pat. No. 4,006,475.
The circuit of U.S. Pat. No. 4,006,475 is shown in FIG. 1 and includes four least significant bits B.sub.0, B.sub.1, B.sub.2, and B.sub.3 input to a 4 bit register 12, called the R.sub.1 register. The binary value of the four LSB's B.sub.0 -B.sub.3 is defined to be L. The four most significant bits are B.sub.4, B.sub.5, B.sub.6, and B.sub.7, and their binary value is defined to be M. They are input to a 4 bit register 24, referred to as the R.sub.2 register. Registers R.sub.1 and R.sub.2 are clocked by a clock signal C.sub.2. The outputs 13 and 25 of registers R.sub.1 and R.sub.2, respectively, are fed into binary adders 14 and 22, respectively. The four outputs of binary adder 14 are input to an accumulator register 16, referred to as the R.sub.3 register, the four outputs 17 of which are fed back into four inputs of binary adder 14. The contents of register R.sub.3 therefore are added to the contents of register R.sub.1. The carry output of binary adder A.sub.1 is fed via conductor 19 to the second binary adder 22 and summed with the MSB's B.sub.4 -B.sub.7, and the results are fed into register 28, referred to as the R.sub.4 register. The R.sub.4 register is a 5 bit register. The five outputs 34 of register R.sub.4 are fed into a 4 bit plus 1 bit seventeen level digital-to-analog converter in which the details of 4 bit plus 1 bit DAC 30 are shown in FIG. 1 of U.S. Pat. No. 4,006,475. The additional bit is a repeat of the LSB. The analog output of digital-to-analog converter 30 is filtered by a low pass filter 32 to produce the analog output voltage on conductor 33.
Combinational gate 20 produces a high output signal in response to a coincidence of high levels of clock signals C.sub.1 and C.sub.2, and applies that output to a strobe input of register R.sub.3. The C.sub.2 clock input is connected to the clock input of register R.sub.3. The C.sub.1 clock input is connected to the clock input of the R.sub.4 register 28.
Every 16 C.sub.1 clock times, C.sub.2 presets register R.sub.3 to a binary 8, i.e., a "1" and three "0"s. The sum of the contents of registers R.sub.3 and R.sub.1 are fed back into register R.sub.3 on the leading edge of each C.sub.1 clock pulse. Every time this sum exceeds a binary 15, a CARRY signal is fed on conductor 19 to binary adder 22 and summed with B.sub.4 -B.sub.7 The output of adder 22 is loaded into output register R.sub.4 at the leading edge of each C.sub.1 clock pulse, and the 5 outputs of register R.sub.4 drive the 4 bit plus 1 bit DAC 28 to produce a pulsed analog waveform 31 which is shown at the bottom of FIG. 2. If there is no carry signal generated by adder 14, the contents of register R.sub.4 is equal to M, the value of the most significant bits B.sub.4 -B.sub.7 of the incoming word. The pulsed analog waveform produced on conductor 31 by DAC 32 is averaged by low pass filter 32 to produce a smooth analog output signal on conductor 33.
It can be shown that the average output voltage value at the output of low pass filter is ##EQU1## which is the desired analog value.
As a result of the interpolation technique used, the DAC shown in the prior art circuit of FIG. 1 inherently requires clocking at the fast C.sub.1 clock rate to get the needed interpolation or averaging. The C.sub.1 pulse rate must be matched by the data produced at the output 31 of the 4 bit plus 1 bit DAC 30. At the present state of the art, it is impractical to obtain conversions that fast for an accurate 18 bit DAC implemented according to U.S. Pat. No. 4,006,475. However, it is desirable in state-of-the-art implementations of digital audio converters to provide conversion at a clock rate of approximately 15 megahertz. Although it is possible to build DACs this fast, the resulting "glitches" due to bit switching make 18 bit accuracy difficult to achieve. MSB transitions in digital-to-analog converters which as a practical matter could be economically used to implement DAC 30 in FIG. 1 result in large perturbations of current summing nodes therein. The resulting long settling times of such DACs make it impractical to achieve the needed 15 megahertz or greater DAC conversion rates. Consequently, the technique disclosed in U.S. Pat. No. 4,006,475 is incapable of achieving the above-indicated performance objectives.